The present invention relates, in general, to the field of reconfigurable processor-based computing systems. More particularly, the present invention relates to a switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element (such as a reconfigurable computing element comprising one or more field programmable gate arrays “FPGAs”) and one or more dense logic devices comprising commercially available microprocessors, digital signal processors (“DSPs”), application specific integrated circuits (“ASICs”) and other typically fixed logic components having relatively high clock rates.
As disclosed in one or more representative embodiments illustrated and described in the aforementioned patents and patent applications, SRC Computers, Inc. proprietary Switch/Network Adapter Port technology (SNAP™, a trademark of SRC Computers, Inc., assignee of the present invention) has previously been enhanced such that the signals from two or more dual in-line memory module (“DIMM”) (or Rambus™ in-line memory module “RIMM”) slots are routed to a common control chip.
Physically, in a by-two configuration, two DIMM form factor switch/network adapter port boards may be coupled together using rigid flex circuit construction to form a single assembly. One of the DIMM boards may also be populated with a control field programmable gate array (“FPGA”) which may have the signals from both DIMM slots routed to it. The control chip then samples the data off of both slots using the independent clocks of the slots. The data from both slots is then used to form a data packet that is then sent to other parts of the system. In a similar manner, the technique may be utilized in conjunction with more than two DIMM slots, for example, four DIMM slots in a four-way interleaved system.
In operation, an interleaved memory system may use two or more memory channels running in lock-step wherein a connection is made to one of the DIMM slots and the signals derived are used in conjunction with the original set of switch/network adapter port board signals. In operation, this effectively doubles (or more) the width of the data bus into and out of the memory. This technique can be implemented in conjunction with the proper selection of a memory and input/output (“I/O”) controller (“North Bridge”) chip that supports interleaved memory.
Currently described in the literature is a reconfigurable computing development environment called “Pilchard” which plugs into a personal computer DIMM slot. See, for example, “Pilchard—A Reconfigurable Computing Platform with Memory Slot Interface” developed at the Chinese University of Hong Kong under a then existing license and utilizing SRC Computers, Inc. technology. The Pilchard system, and other present day systems rely on relatively long column address strobe (“CAS”) latencies to enable the FPGA to process the memory transactions and are essentially slaves to the memory and I/O controller.
With the speed gap ever increasing between the processor speeds and the memory subsystem, processor design has been optimized to keep the cache subsystem filled with data that will be needed by the program currently executing on the processor. Thus, the processor itself is becoming less efficient at performing the large block transfers that may be required in certain systems utilizing currently available switch/network devices.
The need to have a relatively large volume of system dynamic random access memory (“DRAM”) has increased in recent years due to the need to handle ever larger databases and with ever increasing problem sizes. At the same time, integrated circuit memory densities continue to double approximately every eighteen to twenty four months. Consequently, more and more memory devices are required in a system to meet an applications needs.
An even greater impact on the performance of a system has been the ever increasing time (in processor clocks) it takes to access the DRAM in the system. This has created pressure for even faster memory sub-systems. For these reason, the double data rate (“DDR”) DDR2 and DDR3 memory specifications have been set forth. These specifications include clock rates of from 200 to 400 MHz, but yet they do not incorporate modifications to the basic interconnect structure and still impose a stub terminated bus structure. Because of the clock rate involved with this bus structure, the number devices present on the bus is limited, thus creating a situation where the memory needs of the applications being run are still not being met.
For this reason, a new memory bus structure is being developed which is denominated as the Fully Buffered DIMM (FB-DIMM). The FB-DIMM uses an Advanced Memory Buffer (AMB) to perform serial to parallel conversions necessary to enable the memory controller in the North Bridge to function serially. The Advanced Memory Buffer then converts this to the parallel signaling that is required by the standard DDR2 SRAM. The Advanced Memory Buffer also incorporates a pass-through port to enable the use of multiple FB-DIMM's in a given system. With this bus structure, all of the interconnects are essentially point-to-point differential serial. Further, along with the pass-through port, a vary large memory subsystem can be created.